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1. The complement of the function F = (A + B’)(C’ + D)(B’ + C) is:
A’B + CD’ + BC'
AB’ + C’D + B’C
AB’ + CD’ + BC
AB + BC + CD

2. To put the 8085 microprocessor in the wait state
lower the-HOLD input
lower the READY input
raise the HOLD input
raise the READY input

3. Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non­ pipelined but identical CPU, we can say that
T1 <= T2
T1 >= T2
T1 < T2
T1 is T2 plus the time taken for one instruction fetch cycle

4. The 8085 microprocessor responds to the presence of an interrupt
As soon as the TRAP pin becomes 'high'
By checking the TRAP pin for 'high' status at the end of each instruction fetch
By checking the TRAP pin for 'high' status at the end of the execution of each instruction
By Checking the TRAP pin for 'high' status at regular intervals

5. The most appropriate matching for the following pairs X: Indirect addressing 1 : Loops Y: Immediate addressing 2 : Pointers Z: Auto decrement addressing 3: Constants is
X-3, Y-2, Z-1
X-I, Y-3, Z-2
X-2, Y-3, Z-1
X-3, Y-l, Z-2

6. Consider the values A = 2.0 x 10^30, B =-2.0 x 10^30, C= 1.0, and the sequence X: = A + B Y: = A + C X: = X + C Y: = Y + B executed on a computer where floating-point numbers are represented with 32 bits. The values for X and Y will be
X = 1.0, Y = 1.0
X = 1.0, Y = 0.0
X = 0.0, Y = 1.0
X = 0.0, Y = 0.0

7. A low memory can be connected to 8085 by using
INTER
RESET IN
HOLD
READY

8. Suppose a processor does not have any stack pointer register. Which of the following statements is true?
It cannot have subroutine call instruction
It can have subroutine call instruction, but no nested subroutine calls
Nested subroutine calls are possible, but interrupts are not
All sequences of subroutine calls and also interrupts are possible

9. A processor needs software interrupt to
test the interrupt system of the processor
implement co-routines
obtain system services which need execution of privileged instructions
return from subroutine

10. A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged
a hardware interrupt is needed
a software interrupt is needed
a privileged instruction (which does not generate an interrupt) is needed
a non-privileged instruction (which does not generate an interrupt is needed

11. Which is the most appropriate match for the items in the first column with the items in the second column: X. Indirect Addressing I. Array implementation Y. Indexed Addressing II. Writing re-locatable code Z. Base Register Addressing III. Passing array as parameter
(X, III) (Y, I) (Z, II)
(X, II) (Y, III) (Z, I)
(X, III) (Y, II) (Z, I)
(X, I) (Y, III) (Z, II)

12. The 2’s complement representation of (−539)10 in hexadecimal is
ABE
DBC
DE5
9E7

13. A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
INTA is active
HOLD is active
READY is active
None of These

14. The 2' s complement representation of the decimal value - 15 is
1111
11111
111111
10001

15. Sign extension is a step in
floating point multiplication
signed 16 bit integer addition
arithmetic left shift
converting a signed integer from one size to another

16. In 2' s complement addition, overflow
is flagged whenever there is carry from sign bit addition
cannot occur when a positive value is added to a negative value
is flagged when the carries from sign bit and previous bit match
None of the above

17. In the absolute addressing mode
the operand is inside the instruction
the address of the operand is inside the instruction
the register containing address of the operand is specified inside the instruction
the location of the operand is implicit

18. What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program? MVI L, 5DH MVI L, 6BH MOV A, H ADD L
AC = 0 and CY = 0
AC = 1 and CY = 1
AC = 1 and CY = 0
AC = 0 and CY = 0

19. The performance of a pipelined processor suffers if
the pipeline stages have different delays
consecutive instructions are dependent on each other
the pipeline stages share hardware resources
All of the above

20. Horizontal microprogramming :
does not require use of signal decoders
https://compsciedu.com/mcq-questions/Computer-Architecture/GATE-cse-question-paper/8#:~:text=results%20in%20larger%20sized%20microinstructions%20than%20vertical%20microprogramming
uses one bit for each control signal
All of the above

21. Assuming all numbers are in 2's complement representation, which of the following numbers is divisible by 11111011?
11100111
11100100
11010111
11011011

22. For a pipelined CPU with a single ALU, consider the following situations 1. The j + 1-st instruction uses the result of the j-th instruction as an operand 2. The execution of a conditional jump instruction 3. The j-th and j + 1-st instructions require the ALU at the same time Which of the above can cause a hazard ?
1 and 2 only
2 and 3 only
3 only
All of the above

23. Consider the grammar rule E → E1 - E2 for arith­metic expressions. The code generated is targeted to a CPU having a single user register. The sub­traction operation requires the first operand to be in the register. If E1 and E2 do not have any com­mon sub expression, in order to get the shortest possible code
E1 should be evaluated first
E2 should be evaluated first
Evaluation of E1 and E2 should necessarily be interleaved
Order of evaluation of E1 and E2 is of no consequence

24. If 73x (in base-x number system) is equal to 54y (in base-y number system), the possible values of x and y are
8,16
10,12
9.13
8.11

25. Which of the following addressing modes are suitable for program relocation at run time ?
Absolute addressing
Based addressing
Relative addressing
Indirect addressing

26. Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is
1100 0100
1001 1100
1010 0101
1101 0101

27. A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be
120.4 microseconds
160.5 microseconds
165.5 microseconds
590.0 microseconds

28. Spatial locality refers to the problem that once a location is referenced
It will not be referenced again
It will be referenced again
A nearby location will be referenced soon
None of the above

29. The Principle of locality justifies the use of
Interrupts
Threads
DMA
Cache memory

30. A system that has a lot of crashes, data should be written to the disk using?
write – through
write – back
both (a) and (b)
None of the above

31. Which addressing mode is suitable for a high-level language statement?
Auto increment
Indexed
Displacement
Auto decrement

32. Which memory unit has the lowest access time?
Cache
Registers
Magnetic disk
Main memory

33. In a 16-bit instruction code format 3-bit operation code, 12-bit address, and 1 bit is assigned for address mode designation. For indirect addressing, the mode bit is
0
1
Pointer
Off - Set

34. A 32-bit address bus allows access to a memory of capability
64 GB
16 GB
1 GB
4 GB

35. Pipelining improves CPU performance due to?
Reduced memory access time
Increased clock speed
The introduction of parallelism
Additional functional units

36. The system bus consists of
Data bus
Data bus and address bus
Data bus and control bus
Data bus, control bus and address bus

37. An instruction cycle refers to
Fetching an instruction
Clock speed
Fetching, decoding, and executing an instruction
Executing an instruction

38. A hardware interrupt is
Also called an internal interrupt
Also called an external interrupt
An I/O interrupt
A clock interrupt

39. Which of the following is not involved in a memory write operation?
MAR
PC
MDR
Data bus

40. To prevent signals from colliding on the bus, ……………….. Prioritize access to memory by I/o channels and processors.
A register
Interrupts
The processor scheduler
A controller

41. ………… improve system performance by temporarily storing data during transfers s/w devices or processers that operate at different speeds.
Caches
Controllers
Buffers
Registers

42. Addressing mode is …………………
Explicitly specified
Implied by the instruction
Both a and b
Neither a nor b

43. Which of the following is not a valid class of interrupts? 1) Program 2) Timer 3) I/o 4) Hardware failure
1 and 3
1, 2 and 4
2 and 3
None of the above

44. System calls are usually invoked by using 1) An indirect jump 2) A software interrupt 3) Polling 4) A privileged instruction
2 and 3
1 and 3
1, 2, 3 & 4
3 & 4

45. Which of the following holds data and processing instructions temporarily until the CPU needs it??
ROM
Control unit
Main memory
Coprocessor chips

46. Which of the following register processors used for fetch and execute operations? 1) Program counter 2) Instruction register 3) Address register
1 and 3
1 and 2
2 and 3
1,2 and 3

47. Microinstruction length is determined by ……………….. 1) The maximum number of simultaneous micro-operations that must be specified 2) The way in which the control information is represented or encoded 3) The way in which the next microinstruction address is specified
1 and 2
2 and 3
1 and 3
All of the above

48. ID catching system, the memory reference made in any short time integral tends to use only a small fraction of the total memory?
Checker boarding
Locality principle
Memory interleaving
None of the above

49. The word length of a CPU is defined as
The maximum addressable memory size
The Width of a CPU register
The width of the address bus
The number of general purpose CPU registers

50. The register which holds the address of the locating to or from which data are to be transferred is known as
Index register
Instruction register
Memory address register
Memory data register