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GATE STUDY MATERIAL /COMPUTER ARCHITECTURE MCQ SET 3

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1. The register which holds the address of the locating to or from which data are to be transferred is known as




2. Which one is required while establishing the communication link between CPU and peripherals?




3. Which of the following data transfer modes takes relatively more time?




4. Halt operation comes under ………




5. The CPU initializes the DMA by sending ………




6. In four – address instruction format, the number of bytes required to encode an instruction is (assume each address requires 24 bits, and 1 byte is required for operation code)




7. The minimum time delay between the initiations of two independent memory operations is called




8. Consider an algebraic system (A,*), where A is a set of all non-zero real numbers and * is a binary operation defined by A* b = ab/4 then (G*) is a




9. A 2 level memory has an average access time of 30 ns with cache and memory access time as 20 ns and 150 ns respectively. What is the hit ratio?




10. The following are some of the sequences of operations in the instruction cycle, which one is the correct sequence?




11. Horizontal micro construction has which of the following attributes? 1) Short formats 2) Limited ability to express parallel micro-operations 3) Considerable encoding of the control information




12. The register which keeps track of the execution of a program and which contains the memory address of the instruction currently being executed is known as …………




13. Consider the following situation and fill in the blanks: The computer starts the tape moving by issuing a command; the processor then monitors the status of the taps by means of a ………….. When the tape is in the correct position, the Processor issues a ……………




14. For interval arithmetic best rounding technique use is ………..




15. Assume that the time required for the eight functional units, which operate in each of the eight cycles, are as follows. 5us, 8us, 64s, 10us, 15us, 12us, 6us, 8us Assume that pipe lining adds 1 us, of overhead. Find the speedup versus the single cycle data path.




16. Assembler directives represent……………… 1) Machine instructions to be included in the object program 2) The allocation of storage for constants or program variable




17. The bus system of a machine has the following propagation delay times 40 ns for the signals to propagate through the multiplexers, 90ns to perform the ADD operating in the ALU, 30ns delay in the destination decoder, and 20ns to store the data into the destination register. What is the minimum cycle time that can be used for the clock?




18. The sequence of events that happen during a typical fetch operation is ?




19. In a fully associative cache memory consisting of 256 cache lines of 16 bytes each, a tag field is of 14 bits. Determine the size of cache memory and main memory.




20. If doubling the cache line length reduces the miss rate to 3 percent, by how much it reduces the average memory access time?




21. Consider the following register – transfer language: R₃ ← R₂+ M[R₁ + R₂] Where R₁, R₂ are the CPU registers and M is a memory location in primary memory, which addressing mode is suitable for above register transfer language?




22. Booth′s algorithm is used in floating – point




23. A 5 stage pipeline with the stages taking 1, 1, 3, 1, 1 units of time has a through put of a. 1⁄3 b. 1⁄7 c. 7 d. 3




24. A 5 stage pipeline with the stages taking 1, 1, 3, 1, 1 units of time has a through put of




25. What is the control unit’s function in the CPU?




26. In a two-level memory hierarchy, the access time of the memory is 12 nanoseconds and the access time of the main memory is 1.5 microseconds. The hit ratio is 0.98. What is the average access time of the two-level memory system?




27. Consider the following organization of main memory and cache memory. Main memory: 64k ×16 Cache memory: 256 × 16 Memory is word addressable and block size of 8 words. Determine the size of tag field if the direct mapping is used for transforming data from main memory to cache memory.




28. A computer system has 4k – word cache organized in a block – set-associative manner, with 4 blocks per set, 64 words per block, memory is word addressable. The number of bits in the SET and WORD fields of the main memory address format is




29. Booth's coding in 8 bits for the decimal number −57 is:




30. What is the equivalent decimal representation for the following radix representation? (34.44)₈




31. Find x & y values if the following equality is valid. ( X567 )₈ + ( 2YX5 )₈ = ( 71YX )₈




32. How many digits are required to represent 126 bit binary number in decimal?




33. Assuming all numbers are in 2’s complement representation, which of the following numbers is divisible by 11111011?




34. What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding? (113.+−111.)+7.51 113.+(−111.+7.51)




35. (1217)₈ is equivalent to




36. P is a 16 – bit signed integer. The 2’s complement representation of P is (F87B)₁₆. The 2’s complement representation of 8 * p is




37. Find the radix 5 representation for the following decimal representation: (39)₁₀ = ( ) ₅




38. Find the value of radix r, with the following equality is matached. √(21)ᵣ = (11)ᵣ




39. How many bits are needed to represent 20 digit decimal number in binary?




40. Consider the following subtraction and Identify the correct answer. (C012.25)₄ – (10111001110.101)₈




41. Let A = 11111010 and B = 00001010 be two 8 – bit 2's complement numbers. Their product in 2's complement is




42. The range of integers that can be represented by an n – bit 2's complement number system is




43. The switching expression corresponding to f(A, B,C, D) = Σ (1, 4, 5, 9, 11,12) is




44. What is the maximum number of different Boolean functions involving n boolean variables?




45. How many Boolean functions are possible with 2 trinary variables?




46. How many minimum 2-input nor gates are needed to realize A+BC?




47. Which of the following statement is true regarding ‘HAZARD’?




48. The min term expansion of f(P,Q,R) = PQ + QR̅ + PR̅ is




49. How many Boolean functions are possible with 3 Boolean variables such that the number of min terms are either one or two?




50. Which of the following statement is FALSE regarding functionally completeness, (FC).




51. Which of the following is the minimization expression for A+A'B+A'B'C+A'B'C'D?




52. Consider a hypothetical k-map in which essential prime implicants covering all the min – terms except two. Each of the left over min – term is covered by 3 different redundant prime implicants. What would be the no of minimal expressions denoted by the map?




53. The literal count of a Boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of (x y + x z) is 4. What are the minimum possible literal counts of the product – of – sum and sum – of – product representations respectively of the function given by the following karnaugh map? Here, x denotes “don’t care”.




54. What are the essential prime implicants of the following Boolean functions? F (a, b, c) = a'c + ac' + b'c




55. A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.